Recently, a method of forming bipolar transistors using a self-aligning technique has been developed. One such method is disclosed in a pending U.S. Patent Application, entitled "A Polysilicon Self-Aligned Bipolar Device and Process of Manufacturing the Same," filed Nov. 19, 1986, Ser. No. 932,752, the subject matter of which is incorporated herein by reference in its entirety. Double-poly self-aligned transistors use a first polysilicon layer to form the base contacts and a second polysilicon layer to form the emitter contact.
While single polysilicon layer transistors have been developed, the process is not fully self-aligning. Self-alignment allows the spacing between the base and emitter contacts to be minimized, thereby minimizing base resistance and reducing the collector-base junction area. By reducing the junction area, the parasitic capacitance of the device is similarly reduced.
Recently, a transistor has been developed wherein a single polysilicon layer is used for the base and emitter contacts; however, the spacing between the base and emitter contacts is defined by a photomask. Therefore, the spacing between the contacts is limited by the capability of the photolithographic process.
Therefore, a need has arisen for a method of forming a single polysilicon self-aligned transistor structure having minimum separation between the base and emitter contacts.